Backplane Speed
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RGI_Matthew
Backplane Speed
I can't find the documentation that details the backplane speed for the ALOS6850 switch family. I would like to stack two 48 port switches. I would also be interested in understanding the backplane speed as I add more switches to the stack. Thanks in advance.
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one6f
Re: Backplane Speed
Hi,
only OS9600/9700/9800 have a backplane architecture.
For OS6850 raw fabric capacity:
OS6850-48 is 96Gbps full duplex or 192Gbps aggregate
OS6850-48X is 120Gbps full duplex or 240Gbps aggregate
Raw stacking capacity is 24Gbps full duplex (12Gbps StackA + 12Gbps StackB)
Throughput in stacked configuration for 64byte packets
48ports*1Gbps/((8 bits/byte)*(64byte+20byte)) = 48*1,488,095.23 pps= 71,428,571.04pps (approx: 71.4Mpps)
2ports*10Gbps/((8 bits/byte)*(64byte+20byte)) = 2 * 14,880,952.3 pps= 29,761,904.6pps (approx: 29.8Mpps)
OS6850-48 (48 GE ports + 2 10G stacking): 101.2Mpps
OS6850-48X (48 GE ports + 2 10G uplinks + 2 10G stacking): 131Mpps
For 1518byte packets accordingly:
OS6850-48 (48 GE ports + 2 10G stacking): 5.52Mpps
OS6850-48X (48 GE ports + 2 10G uplinks + 2 10G stacking): 7.14Mpps
only OS9600/9700/9800 have a backplane architecture.
For OS6850 raw fabric capacity:
OS6850-48 is 96Gbps full duplex or 192Gbps aggregate
OS6850-48X is 120Gbps full duplex or 240Gbps aggregate
Raw stacking capacity is 24Gbps full duplex (12Gbps StackA + 12Gbps StackB)
Throughput in stacked configuration for 64byte packets
48ports*1Gbps/((8 bits/byte)*(64byte+20byte)) = 48*1,488,095.23 pps= 71,428,571.04pps (approx: 71.4Mpps)
2ports*10Gbps/((8 bits/byte)*(64byte+20byte)) = 2 * 14,880,952.3 pps= 29,761,904.6pps (approx: 29.8Mpps)
OS6850-48 (48 GE ports + 2 10G stacking): 101.2Mpps
OS6850-48X (48 GE ports + 2 10G uplinks + 2 10G stacking): 131Mpps
For 1518byte packets accordingly:
OS6850-48 (48 GE ports + 2 10G stacking): 5.52Mpps
OS6850-48X (48 GE ports + 2 10G uplinks + 2 10G stacking): 7.14Mpps
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RGI_Matthew
Re: Backplane Speed
Thanks for replying so quickly. Is this information available in a quick reference for each switch family? We are looking to upgrade the switches and this would be extremely useful
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one6f
Re: Backplane Speed
No, you can retrieve this information via your business partnerRGI_Matthew wrote:Is this information available in a quick reference for each switch family?
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devnull
Re: Backplane Speed
Does anyone have information about how stacking works in ALU Switches?
For example: Cisco has a whitepaper (http://www.cisco.com/en/US/prod/collate ... b096a.html), where i learned, that the old stacking technology (Stackwise) sends each packet around the whole stack ring, even when it should only be send from port 1/1 to 1/2.
With stackwise+ the switches support local switching and destination striping, which frees up space on the stackcable.
Without that (so old technology) a complete Cisco stack is limited to 16Gb/s/32Gb/s Full duplex in total..
So what exactly is alcatel doing, local switching? Every packet on Stack ring? Destination Striping? When using stackcables is the backplane the 24GBit for the whole stack?
Do i still have wirespeed switching, when my src/dst. hosts are on one stack member?
For example: Cisco has a whitepaper (http://www.cisco.com/en/US/prod/collate ... b096a.html), where i learned, that the old stacking technology (Stackwise) sends each packet around the whole stack ring, even when it should only be send from port 1/1 to 1/2.
With stackwise+ the switches support local switching and destination striping, which frees up space on the stackcable.
Without that (so old technology) a complete Cisco stack is limited to 16Gb/s/32Gb/s Full duplex in total..
So what exactly is alcatel doing, local switching? Every packet on Stack ring? Destination Striping? When using stackcables is the backplane the 24GBit for the whole stack?
Do i still have wirespeed switching, when my src/dst. hosts are on one stack member?
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one6f
Re: Backplane Speed
Hi,
an Alcatel switch provides distributed processing as system architecture, each module have a high perform. CPU, which are responsible for most operations. There are a FBUS+ for data communication 12Gbps FD and Burst Bus for for controlling(arp, stp bpdu...). During the MAC DA Lookup process if MAC DA unknown MAC SA will be learned on flooding by other NIs, such by cisco. But if MAC DA is know then NI MAC Table sync global PortId and will not be flooded through stack. Unfortunately I don't know any white papers for AOS switches with detailed specific mechanisms as you provided for Cisco. There are some boilerplate infos, guides or recommendations for internal use only.
an Alcatel switch provides distributed processing as system architecture, each module have a high perform. CPU, which are responsible for most operations. There are a FBUS+ for data communication 12Gbps FD and Burst Bus for for controlling(arp, stp bpdu...). During the MAC DA Lookup process if MAC DA unknown MAC SA will be learned on flooding by other NIs, such by cisco. But if MAC DA is know then NI MAC Table sync global PortId and will not be flooded through stack. Unfortunately I don't know any white papers for AOS switches with detailed specific mechanisms as you provided for Cisco. There are some boilerplate infos, guides or recommendations for internal use only.
